1. Field of the Invention
The present invention relates to a sample-and-hold circuit.
2. Description of the Related Art
Various types of sample-and-hold circuits are known. Of these circuits, the "diode-bridge sample-and-hold circuit" can operate at high speed with high accuracy.
The conventional diode-bridge sample-and-hold circuit has an input terminal 505, an output terminal 506, a capacitor 507 connected to the output terminal 506, three constant-current source circuits 508 to 510, two transistors 511 and 512 used as switching transistors, and a diode-bridge circuit as shown in FIG. 12. The diode-bridge circuit comprises four diodes 501 to 504. The common node of the first and second diodes 501 and 502 is connected to the input terminal 505, and the common node of the second and third diodes 503 and 504 is connected to the output terminal 506. The common node of the first and third diodes 501 and 503 is connected to the first constant-current source 508 and also to the collector of the first switching transistor 511. The common node of the second and fourth diodes 502 and 504 is connected to the second constant-current source circuit 509 and also to the collector of the second switching transistor 512. The emitters of both switching transistors 511 and 512 are connected to the constant current-supply circuit 510. Two clock signals 513 and 514 180.degree. out of phase with respect to each other, are input to the bases of the transistors 511 and 512, respectively. The transistors 511 and 512 are thereby operated in opposite phases, whereby the sample-and-hold circuit can operate in two modes, i.e., sample mode and hold modes.
When the clock signals turn the first and second transistors 511 and 512 off and on, respectively, the sample-and-hold circuit is set in the sample mode. More precisely, once the first and second transistors 511 and 512 are turned off and on, respectively, the current Ibias supplied from the third constant-current source circuit 510 flows through the second switching transistor 512, biasing all diodes 501 to 504. If the signal at the input terminal 505 is constant with respect to time, the current Ibias/2 from the first constant current-source circuit 508 divides equally between the first and second diodes 501 and 502, and the third and fourth diodes 503 and 504, such that Ibias/4 flows through each of the diodes 501 to 504. This current combines with the current Ibias/2 supplied from the second constant-current source circuit 509 to equal the current drawn by current source 510 through transistor 512, Ibias. As a result, no output current "Is" flows to the output terminal 506, and the potential at the capacitor 507 connected to the output terminal 506 does not change. Further more, the voltage at the output terminal 506 equals the voltage at the input terminal 505 because the voltage drop across diodes 502 and 504, and diodes 501 and 503 are equal due to their equal bias currents.
If the voltage at the input terminal 505 is increased at a sufficient rate with respect to time, the current from the input signal source increases the current through the second diode 502 to greater than Ibias/2 and decreases the current through the first diode 501 to less than Ibias/2 by equal amounts, by half of the amount supplied by the input signal source. Since the current flowing through the second switching transistor 512 is Ibias and the current supplied by the current source 509 is Ibias/2, the sum of the currents flowing through the diodes 501 and 504 must equal Ibias/2. Likewise, since no current is drawn by the transistor 511 and the current supplied by the current source 508 is Ibias/2, again, the sum of the currents flowing through the diodes 502 and 503 must equal Ibias/2. In other words, the current flowing through the first diode path of diodes 501 and 502 is equal to that flowing through the second diode path of diodes 503 and 504 and in each case equals Ibias/4. Hence, as the current flowing through the second diode 502 increases, the current through the diode 504 must decrease by the same amount that the current through the diode 502 increases. Likewise, as the current through the diode 501 decreases, the current through the diode 503 must increase by the same amount that the current through the diode 501 decreases. The resulting difference in current between the diodes 503 and 504, "Is", charges the capacitor 507 until its voltage, the output terminal 506, is equal to that of the input terminal 505. At this point, the voltage drop across the diodes 501 to 504 become equal, and their difference in currents become zero, thus, "Is" becomes zero and the circuit achieves a stable condition.
Similarly, if the voltage at the input terminal 505 is decreased at a sufficient rate with respect to time, the current drawn by the input signal source decreases the current through the second diode 502 to less than Ibias/2 and increases the current through the first diode 501 to greater than Ibias/2 by equal amounts, by half of the amount drawn by the input signal source. As mentioned previously, the sum of the currents flowing through the diodes 501 and 504 must equal Ibias/2, and the sum of the currents flowing through the diodes 502 and 503 must equal Ibias/2. As the current flowing through the second diode 502 decreases, the current through the diode 504 must increase by the same amount that the current through the diode 502 decreases. And, as the current through the diode 501 increases, the current through the diode 503 must decrease by the same amount that the current through the diode 501 increases. The resulting difference in current between the diodes 503 and 504, "Is", discharges the capacitor 507 until its voltage, the output terminal 506, is equal to that of the input terminal 505. Again, the voltage drop across the diodes 501 to 504 become equal, and their difference in currents become zero, thus, "Is" becomes zero and the circuit achieves a stable condition.
It is important to understand that the charging-discharging current "Is" is equal to the input signal source current flowing into and out of the input terminal node 505. Furthermore, the maximum "Is" flows when the diodes 501 and 504 are off for an increasing input signal, or when the diodes 502 and 503 are off for a decreasing input signal. In the case of an increasing input signal, since the diode 501 is off, all of the current supplied by current source 508 flows into the diode 503. Since the diode 504 is off, the current through the diode 503 becomes "Is" and thus, the maximum value "Is" can achieve is Ibias/2. Likewise, for a decreasing input signal, the maximum value "Is" can achieve for discharging is also Ibias/2.
As can be understood from the above, when the first and second transistors 511 and 512 are turned off and on, respectively, the sample-and-hold circuit is set into the sample mode. Conversely, when the first and second transistors 501 and 502 are turned on and off, respectively, the first to fourth diodes 501 to 504 are turned off, essentially decoupling the input terminal 505 from the output terminal 506, maintaining the potential of the capacitor 507. In this case, the sample-and-hold circuit is set into the hold mode.
The conventional diode-bridge sample-and-hold circuit, however, has the following drawbacks.
First, its slew rate is insufficient, limited by the bias current Ibias/2 of the switching diodes. The bias current supplied to the diodes is usually small in order to reduce the power consumption of the sample-and-hold circuit and, more importantly, to decrease the DC sample pedestal offsets of the sample-and-hold circuit.
Secondly, the input impedance of the sample-and-hold circuit varies drastically when the operating mode is switched from the sample mode to the hold mode, and vice versa. This is because, in the diode bridge circuit, the input diodes 501 and 502 which are on in the sample mode are switched off i.e., open circuit, in the hold mode. To reduce the effect of the varying input impedance, a input buffer circuit is often added in front of the diode bridge circuit. This buffer circuit, however, increases the power consumption and noise of the circuit.
Thus the conventional diode-bridge sample-and-hold circuit suffers from two drawbacks, namely, insufficient slew rate and a drastically varying input impedance.